In VLSI technology, scaling of device (transistor) dimensions is one of the very important and talked about issues. Scaling means reducing the length of channel between drain and source in MOSFET (metal-oxide-semiconductor field-effect transistor). Figure below shows the effective length of the channel as L_eff. If you see a VLSI trend of last 15 years or so you will observe that the length of the channel has been scaled down from 180nm to 14nm in many commercial applications and upto 1nm transistors have been produced in research labs.

There are obvious benefits of reducing the size of transistor because as the size of transistor reduces it becomes possible to pack more number of transistors in same chip area. This gives immense benefits in terms of reduction in cost, more functionality and faster response. However there are obvious challenges faced when the size of the transistor is reduced to such extreme limits. With continuous downscaling of device dimensions, conventional bulk MOSFETs experience increased off state leakage and other undesired short channel effects (SCEs). Various multi-gate devices have proven themselves to be successful in overcoming these challenges. Other than just providing an excellent control over SCEs, Multigate structures give an advantage over single gate MOSFETs in terms of low subthreshold leakage, optimized ON - current, an ideal 60mV/decade slope etc. Nevertheless, as device dimensions enter 10nm or below regime, formation of ultrasharp abrupt junctions imposes a heavy thermal budget on the device structure as annealing becomes quiet tricky and expensive at such small dimensions. Also, extremely precise doping techniques are required to help prevent diffusion of source/drain impurities into the channel. Therefore, as an alternative, Junctionless (JL) devices are being modelled and fabricated. The concept of Junctionless Transistor was first given by Lilienfeld in 1925 but remained unexplored for many decades to follow until J.P. Colinge and his research group at Tyndall National Institute in Ireland developed and demonstrated the working of first ever successful Junctionless transistor in the year 2009.

Junctionless Transistor

JL transistor as shown in figure above is fundamentally a heavily doped nanowire in a uniform fashion with no abrupt source/drain junctions and no doping concentration gradients. Heavy doping of device ensures a reasonably good amount of current flow across it when the device is turned 'ON'. However, it tends to reduce the carrier mobility which harms the transconductance of the device. The semiconductor layer forming the device should ideally be narrow and thin so that the charge carriers get fully depleted when it is turned 'OFF'. The conduction mechanism it supports is bulk conduction and not traditional surface channel conduction. This helps JL devices in achieving a better control over prodigious SCEs and thus it shows a decent scalability below 10nm.

So with the need for the reduction of device dimensions in VLSI technology, the MOSFET is evolving to overcome the design barriers and to deliver the desired performance.

By - Dhriti Duggal, Assistant Professor (ECE), Chitkara University, H.P.

References:-

1. http://physicsworld.com/cws/article/news/2010/mar/01/junctionless-transistor-makes-its-debut
2. S. I. Amin and R. K. Sarin, "Junctionless transistor: A review," Third International Conference on Computational Intelligence and Information Technology (CIIT 2013), Mumbai, 2013, pp. 432-439.
3. A. Kranti et al., "Junctionless nanowire transistor (JNT): Properties and design guidelines," 2010 Proceedings of the European Solid State Device Research Conference, Sevilla, 2010, pp. 357-360.